1. Field of the Invention
The present invention relates generally to data processing which is performed using a large-capacity main storage device and, more particularly, to a method of and an apparatus for effecting data processing both of which are suitable for the extension of the length of a storage address and assuring compatibility with a conventional type of data processor.
2. Description of the Prior Art
A typical technique of extending the length of main storage addresses used in a data processor is discussed in a manual provided by IBM, "IBM System/370, Extended Architecture Principles of Operation (1983), pp. 5-4 to 5-10 and pp. 7-1 to 7-8". This prior art adopts a so-called virtual storage system which includes two kinds of mode of address virtual length, i.e., 24-bit and 31-bit modes and in which fixed point data and logic data have a data of length of a word, that is, 32 bits. A word is a basic building block of a data. Each of a plurality of general registers employed has a length of 32 bits, and data arithmetic or logic operation instructions such as addition and subtraction of data are prepared for the entire 32 bits of each of the general registers. However, since no address operation instruction dedicated to an arithmetic or logic operation of an address is prepared, arithmetic or logic operations on addresses are performed by means of the data operating instructions. During the execution of the data operation instructions, the entire 32 bits of any of the general registers is read out, and an arithmetic or logic operation is performed on the 32-bit data. The 32-bit result of the arithmetic or logic operation is written into one of the general registers. An instruction for accessing a main storage for an operand held therein specifies two general registers serving as a base register and an index register, respectively, both of which are used in generating the address of the operand . A virtual address for main-storage access is generated by adding the contents of the base register and the index register to a displacement included in the instruction code. In this case, if the length of the result of addition exceeds the length of the virtual address predetermined by a current mode of virtual address length, the excessive higher-order portion of the result is ignored. Therefore, such addition is commonly performed by reading out only the number of bits equivalent to the length of the virtual address for a current virtual address length mode from the base and index registers. More specifically, higher-order 24 bits upward from the least significant bit of the base or index register is read out in a 24-bit mode, and, in a 31-bit mode, the read out of higher-order 31 bits upward from the least significant bit is effected. A load instruction serving as one of the main-storage access instructions specifies the action of reading 32-bit data out of the main storage specified by the thus-generated address irrespective of the mode of the virtual address length, such read out data being written into the entire 32-bit field of a general register.
The virtual address length mode is specified by a 1-bit mode in a register holding a program status word indicating the status of various conditions in the processor. The mode bit can be changed by a mode change/branch instruction. The virtual address length mode is changed by changing the mode bit.
As described above, however, the prior art takes no account of the case where the length of an address is extended so greatly that the extended length of the address exceeds the length of data which is not extended, that is, the number of bits or length of a bit string of the general register. In such a case, if the prior art is used, it is required to extend the data length to a size equal to or greater than the extendedlength of the address so as to use data operation instructions for the purpose of executing arithmetic or logic operations on the extended data length.
However, extension of the data length would make it difficult to perform data transfer between an old program formulated before the data extension and a new program formulated after the same. For instance, if the non-extended length of data is 32 bits in the old program and the extended length of data in the new program is 64 bits, the 32-bit data must be converted to the 64-bit data so as to enable data transfer from the old program to the new program. This leads to a problem in that the extension of data length makes is difficult to assure compatibility between various data processors.
Another technique of extending the length of main storage addresses is shown in Japanese published laid-open patent application (Kokai tokkyo koho) 54-95129, wherein a data processor includes a circuit for generating an extended length address of 32 bits by use of general purpose registers of 32 bits so as to enable execution of instructions prepared for a main storage which is accessible by 24 bit addresses.
In this prior art it is disclosed that an extended-length address includes significant 24 bits at its lower bit portion and 8 bits of all zero at its upper bit portion, when the extended-length address is to be used to fetch an instruction from a main storage. Thus, this prior art enables the data processor to use already made control programs (operating system program) with less change.
In this prior art, however, length of data fetched from or stored into the main storage is presumed to be 32 bits. That is, the extended address does not still exceed the data length.
Therefore, this prior art has the same problem as mentioned above regarding the previously mentioned prior art.